Deterministic access protocol local area network

ABSTRACT

A data controller to control passage of data between a plurality of data handling devices comprises a communication link to permit communication of the devices with one another. An indicator is associated with each of the devices to indicate data is to be transmitted from any one of the devices. An inhibitor operates upon a device after it transmits data to inhibit access of that device to the communication link and to the indicator. A reset device is responsive to the indicator to remove the inhibitor when the indicator indicates that no data is to be transmitted.

The present invention relates to data controllers to control the passageof data between a plurality of data handling devices.

Data handling devices are now commonly connected in a network to allowthe passage of data between various devices. The network can take one ofseveral forms but each requires a controller to control access to thecommunication link between the data handling devices to ensure that onlyone data message at a time is transferred between the devices. Thecontroller is operable once data is being transmitted to inhibit accessof other devices to the communication link or to abort disrupted data.The devices conventionally are arranged to continue to attempttransmission on a periodic basis until they are successful in gainingaccess to the communication link.

Such an arrangement has proven satisfactory but at higher data handlingrates it is statistically possible that a device can never gain accessto the communications link. Certain applications require a maximum timefor a device to gain access to the communication link, that is theyrequire the system to be deterministic, to ensure that data will becommunicated from one device to another device within a finite time.

It is therefore an object of the invention to provide a data controllerfor use in a network that provides a finite time in which transmissionof data will occur and to ensure each handling device requesting accessto the communication link will achieve a communication link before anyone of the handling devices gains access to the communication link for asecond time.

According, therefore, to the present invention there is provided a datacontroller to control passage of data between a plurality of datahandling devices comprising communications means to permit communicationof said devices with one another, indicator means associated with eachof said devices to indicate data is to be transmitted from any one ofsaid devices, inhibit means operable upon a device after transmission ofdata thereby to inhibit access of that device to said communicationmeans and to said indicator means and reset means responsive to saidindicator means to remove said inhibit means when said indicator meansindicates that no data is to be transmitted thereby preventing thatdevice from gaining multiple access to said communication means untileach of said other requesting devices have gained access to saidcommunication means.

An embodiment of the invention will now be described by way of exampleonly in which

FIG. 1 is a schematic representation of a network

FIG. 2 is a schematic representation of a controller for use with thenetwork shown in FIG. 1

FIG. 3 is a detailed view of one of the components shown in theschematic representation of FIG. 2

FIG. 4 is a schematic representation of a further component shown in therepresentation of FIG. 2

FIG. 5 is a schematic representation of a further component of thesystem shown in FIG. 2.

A local area network 10 is arranged in a tree or star format andcomprises a number of data handling devices 12, each of which isconnected by a transmission link 13 to a selector 14 of a central hub16. The selector 14 is connected through a nexus 18 to a broadcaster 20,which in turn is connected through transmission links 22 to each of thedata handling devices 12.

The selector 14 is operable to select one of the handling devices 12 toreceive data through the associated transmission link 13 and broadcastit through each of the links 22 by way of the broadcaster 20. In thisway, data from one of the devices 12 can be communicated to each of thedevices 12.

To ensure that only one data message is transmitted, selector 14includes one selection device 24 per transmission link 13, and anarbitrator 26 as shown in FIG. 2. The selection device 24 is identicalin many ways to that described in U.S. Pat. No. 4,570,162, issued to thepresent applicants, the contents of which are incorporated herein byreference.

Each of the transmission links 13 is connected through a switch 28 tothe nexus 18. Operation of the switch 28 is controlled by a selectiondevice 24 and is operable to pass data from the link 13 to the nexus 18only upon enablement by the selection device 24. Each transmission link13 is also connected to a distinct data detect function 30 whose output32 is connected to a request function 34. The output of the requestfunction 34 is applied to the arbitrator 26. The arbitrator 26 receivesan input from the request function associated with each of thetransmission links 13 and determines which of the links 13 will beselected for transmission through the nexus 18.

The arbitrator 26 has a plurality of outputs 36 each of which isconnected to a respective one of selection devices 24, and an output 38that is connected to all of the selection devices 24 and provides a busysignal to each of the selection devices.

The selected output 36 and the busy signal 38 are applied to a switchfunction 40 to indicate that the link 13 associated with that particularselection device 24 has been selected. The output of switch function 40is applied to the switch 28 and to a switch 42 that receives a furtherinput from the data detect output 32. The output of switch 42 controlsthe operation of an interlock function 44, which also is connected tothe data detect output 32. The output of the interlock function 44 isapplied to the request function 34 and to switch 28 to enable the switchand allow data to be transmitted from the link 13 to the output 18. Theinterlock 44 inhibits the request function from operating until afterthe nexus 18 has become idle as indicated by the busy signal 38 and anew transmission of data has been detected by the data detect function30. In this way the transmission of a partial packet of data is avoided.

The construction and operation of the components described above isdescribed in further detail in U.S. Pat. No. 4,570,126 and therefore itis not believed to be necessary to describe them further at this time.

To ensure that the selector 14 is deterministic, each selection device24 includes a state holder function 48 that combines an inhibitorfunction 50 and state indicator function 52. The output 32 of datadetect function 30 is applied to the state indicator 52 whose output isapplied as one of the inputs to a switch 54. The switch 54 receivesinputs from the state indicators of all selection devices 24 and asignal from the busy line 38. The output of switch 54 is applied to areset function 56 whose output is connected to the inhibitor 50 in eachof the selection devices 24. The reset function 56 also receives aninput from a timer 58.

The selected signal 36 is applied to the inhibitor 50 and stateindicator 52, and the output of inhibitor 50 is applied to the switch 42by way of connector 49 to inhibit operation of that switch.

As may be seen in FIG. 3, the inhibitor 50 includes an AND gate 60 and aJK Flip-Flop 62. The inputs to the AND gate 60 are derived from theinverted output of the reset function 56 and from the Q output of the JKFlip-Flop 62. The output of AND gate 60 is applied to the K input ofFlip-Flop 62. The J input to Flip-Flop 62 is derived from the output ofan AND gate 64 in the state indicator 52, AND gate 64 receives as one ofits inputs the selected signal 36 and as its other input the Q output ofa JK Flip-Flop 66. The Flip-Flop 66 receives the output of AND gate 64at its K input and the output of an AND gate 68 at its J input.

The AND gate 68 receives one input from the output 32 of data detectfunction 30 and as its other input the Q output of a further JKFlip-Flop 70. The K input to Flip-Flop 70 is connected to the J input ofFlip-Flop 66 with the J input to Flip-Flop 70 being connected to theoutput of AND gate 60 on the inhibitor 50. The output of JK Flip-Flop 66is also applied to the switch function 54.

As may be seen in FIG. 4, the switch function 54 is essentially an ORgate 72 that receives inputs from each of the JK Flip-Flops 66 and thebusy signal 38. The output of OR gate 72 is passed through an AND gate74 to the input of a JK Flip-Flop 76 both forming part of the resetdevice 56. The K input to Flip-Flop 76 is derived directly from theoutput of AND gate 74 and the J input is the inverted output of AND gate74. The output of the reset device 56 utilizes the Q' output which isapplied as the input to the AND gate 60 in FIG. 3.

The AND gate 74 receives as one of its inputs the output of OR gate 72and as the other input the inverted output of the timer 58 indicated infurther detail on FIG. 5. The timer 58 includes a binary down counter 78that is loaded by a signal appearing on the busy line 38. The output(count =0) of binary counter 78 is applied directly to the J input of aJK Flip-Flop 80 and inverted and applied to the K input of the sameFlip-Flop. The inverted output is also applied as one input to an ANDgate 82 which receives as its other input the Q output of Flip-Flop 80.The output of AND gate 82 is applied to the inverted input of the ANDgate 74.

The operation of the data controller will now be described, assuming thenetwork is at idle, that is no data is being transmitted and that nodate is available for transmission. In this situation, all the datadetect outputs 32 are low, or de-asserted, and all the inputs to switch54 are also low, or de-asserted The busy line 38 is also low and theoutput of reset 56 is low. Referring to FIG. 3, the Q outputs of each ofthe JK Flip-Flops 62, 66 are low but the Q output of Flip-Flop 70 ishigh, providing one high input to AND gate 68.

Upon the detection of a transmission from one of the data handlingdevices 12 through the link 13, the associated data detect function 30asserts the signal on output 32 which is passed through request function34 to the arbitrator 26. As there are no other requests received atarbitrator 26 the request is accepted and the selected line 36corresponding to the link 13 is asserted together with the busy line 38to enable switch 40. Because the request is accepted at the start ofdata transmission, the interlock 44 is idle so that switch 28 receivestwo enabling signals to allow it transmit data from the link 13 to thenexus 18.

The assertion of output 32 causes the state holder 48 to change from an"idle" to a "contention" condition. This results in a high output fromthe state indicator 52 to the switch function 54 to indicate thattransmission of data has been requested. As will be appreciated fromFIG. 3, the presence of a high signal at output 32 results in an outputfrom AND gate 68 so that at the next clock cycle the Q output ofFlip-Flop 66 is asserted. As may be seen from FIG. 4, the assertionthrough output from state indicator 52 and through the busy line 38produces a high signal from OR gate 72 which, in turn, produces a highoutput from AND gate 74 as the low output from the timer 58 is invertedat one input to AND gate 74. The high output of AND gate 74 produces lowand high outputs at the J and K inputs of Flip-Flop 76, respectively, toproduce a high output at the Q' gate of reset function 56 at the nextclock cycle. The asserted output from the reset 56 is applied to theinverted input of AND gate 60 so that a low output is obtained forapplying to the K input of Flip-Flop 62.

If the data detect function output 32 goes low, the output of AND gate68 reverts to a low condition but the Q output of Flip-Flop 66 remainshigh to continue to assert an input to the switch function 54. However,the presence of a high signal at the K input to Flip-Flop 70 when datadetect line 32 is high causes the Q output to go low, providing a lowinput to AND gate 68 to disable the AND gate until the Q output fromFlip-Flop 70 is reset to high. This prevents a further high signal beinggenerated by Flip-Flop 66 until the reset function 56 resets Flip-Flop70.

The output to Flip-Flop 66 is de-asserted upon a selected signal beingreceived on line 36 to the input of AND gate 64. The other input to ANDgate 64 is high by virtue of the assertion of the output of Flip-Flop 66so that a high output is obtained from AND gate 64 and asserted againstthe J input of Flip-Flop 66. Upon the next clock pulse, regardless ofthe state of the J input to Flip-Flop 66, the assertion of a high signalat the K input causes the Q output to revert to a low condition,therefore de-asserting the input to switch function 54. At the sametime, a high output from AND gate 64 is applied to the J input ofFlip-Flop 62 and the Q output of Flip-Flop 66 goes high to provide ahigh inhibit output to switch 42. This prevents further processing ofdata through the request function 34.

The output from switch function 54 remains asserted whilst data is beingtransmitted by virtue of the busy signal 38. Once transmission of datahas been completed, and assuming that no other link 13 has attempted togain access during the transmission of that data, all the inputs to ORgate 72 are low, causing a low output from the OR gate 72. This causesthe J input of Flip-Flop 76 to be asserted causing the Q' output tochange from high to low. The low signal is applied to the inverted inputto AND gate 60, which, together with the high output from Flip-Flop 62,provides a high signal at the K input to Flip-Flop 62. Upon the nextclock pulse the Q output of Flip-Flop 62 will be de-asserted to releasethe inhibit signal on switch function 42. The high output from AND gate60 is also applied to the J input of Flip-Flop 70 so that the Q outputreverts to high condition at the next clock pulse. This is applied toone of the inputs of AND gate 68 so that upon the next data detectionsignal on line 32 the state indicator 52 will be conditioned to"contention".

If, during the course of transmission of data, an attempt is made totransmit data from another of the data handling devices 12, the stateindicator 52 associated with that device will assert an output to theswitch 54. Thus, upon completion of transmission by one of the datahandling devices, the output of the OR gate 72 remains high so that theQ' output from Flip-Flop 76 remains low. This then prevents theFlip-Flop 62 from being reset to de-assert the inhibit output to switch42. This condition will remain until each of the inputs to the switchfunction 54 have been de-asserted indicating that data from the deviceassociated with that state indicator has been selected and allowing theoutput from Flip-Flop 76 to return to a high condition and remove eachof the inhibiting outputs from the respective Flip-Flops 62.Accordingly, it will be appreciated that each link is assured to accessto the nexus 18 in a finite time and the nexus 18 cannot be occupied byrepetitive transmissions from other data handling devices.

To ensure that the network 10 is not disabled by a malfunction in one ofthe data handling devices that results in a continuous assertion againstswitch 54, the timer of FIG. 5 is used to reset the inhibit functions 50after a predetermined period. This period is chosen to be slightlylonger than the retry period for each of the devices 12. The timer inFIG. 5 functions to load the binary counter 78 and initiate down countof that counter upon termination of the busy signal in line 38. If asignal is asserted at switch 54, under normal operation the deviceassociated with that signal would attempt to gain access to the nexus 18during the period being counted by the counter 78. Upon gaining access,the line 38 would revert to a busy condition and reload the counter,holding it until the busy signal again is de-asserted. If the countercompletes its count prior to the reassertion of the busy signal 38, theFlip-Flop 80 and AND gate 82 provide a pulse to the inverted input ofAND gate 74. This causes the output of 74 to go low and reset Flip-Flop76 to a low condition. This is then applied to the AND gate 60 to resetFlip-Flop 62 and remove the inhibit signals from the switches.Thereafter, the output of AND gate 82 reverts to a low condition toallow the AND gate 74 to function in response to the output from OR gate72.

It will be seen, therefore, that by monitoring the data detect signaland providing an indication that data transmission is required, it ispossible to ensure that requests made during data transmission are dealtwith prior to any new requests from a device that has already beentransmitted. Whilst it will be appreciated that the operation has beendescribed with respect to the selection device 24 described in theabove-referenced U.S. patent, it is equally applicable to otherselection devices where the indicator and inhibitor can be utilized toinhibit the operation of the equivalent of the selection device 24 untilall requests have been dealt with.

We claim:
 1. A data controller to control passage of data between aplurality of data handling devices comprising communication means topermit communication of said devices with one another, indicator meansassociated with each of said devices to indicate data is to betransmitted from any one of said devices, inhibit means operable upon adevice after transmission of data thereby to inhibit access of thatdevice to said communication means and said indicator means and resetmeans responsive to said indicator means .Iadd.including a means tomonitor each of said indicator means and provide a first signal tomaintain said inhibit means when at least one of said indicator meansindicates data is to be transmitted and a second signal .Iaddend.toremove said inhibit means when .Iadd.each of the plurality of.Iaddend.said indicator means .[.indicates.]. .Iadd.indicate.Iaddend.that no data is to be transmitted, thereby preventing thatdevice from gaining multiple access to said communication means untileach of said other requesting handling devices have gained access tosaid communication means.
 2. A data controller according to claim 1including override means operable upon said reset means after apredetermined period.
 3. A data controller according to claim 1 whereinsaid indicator means includes a plurality of state indicators eachassociated with a respective one of said devices and having anindication output changeable from a first condition to a secondcondition upon data being transmitted by the respective device.
 4. Adata controller according to claim 3 wherein said indication output ofsaid state indicator is changed from said second condition to said firstcondition upon reception of an access acquired signal indicating thatthe respective one of said devices has been connected to saidcommunication means.
 5. A data controller according to claim 4 whereinsaid indication output initiates operation of said inhibit means. .[.6.A data controller according to claim 4 wherein the indication outputs ofeach of said state indicators are applied to said reset means, operationof said reset means being prevented by any of said indication outputsmaintaining said second condition..].
 7. A data controller according toclaim .[.6.]. .Iadd.5 .Iaddend.wherein operation of said reset means isprevented during transmission of data on said communication means.
 8. Adata controller according to claim .[.6.]. .Iadd.5 .Iaddend.furtherincluding override means operable upon said reset means after apredetermined period.